It is understood that conventional passive components, such as capacitors, resistors or inductors, are separately manufactured to be individual passive components for mounting on a substrate. In order to answer the strict requirements including electrical conductivity and elements simplification in the semiconductor packaging field, the passive components, especially capacitor, should be integrated into a printed circuit board (IC substrate).
A method for manufacturing a multi-layer substrate with embedded capacitor is disclosed in R.O.C. Taiwan Patent No. 440,993. A plurality of through holes are formed in a dielectric layer and pass through upper/lower metal layers. The lower metal layer is used as a ground layer without traces. A medium material is filled into the holes of the dielectric layer and the upper metal layer. Then the upper metal layer is etched to form traces. It is essential that a plating layer is formed on the upper metal layer by copper plating to cover the holes of the upper metal layer in order to form embedded capacitors. In accordance with this known manufacturing method, the upper/lower metal layers on the dielectric layer cannot directly provide the upper/lower electrode pads of the embedded capacitors due to the holes. Moreover it is difficult to manufacture the plating layer covering the medium material to be flat, that is because that the filling quantity of the medium material in each hole cannot be controlled to be equal and even. Therefore, the plating layer and the upper metal layer having holes are combined as upper electrode pads of the embedded capacitors, the holes of the upper metal layer change the shape of the upper electrode pads like “II” shaped in cross-section. The value of the embedded capacitor is unable to be controlled, thereby affecting the capacity of build-in capacitor.
Another printed circuit board with embedded capacitor is disclosed in U.S. Pat. No. 6,021,050. Referring to FIG. 1, the printed circuit board (PCB) 100 includes a plurality of glass fiber reinforced resin layers 111, 112, 113. A plurality of intermediate layers 121, 122, such as B-stage thermal setting resin, are provided and placed between the resin layers 111, 112, 113 in order to compress and adhere the resin layers 111, 112, 113 together. Furthermore, a plurality of via holes 160 are formed in the PCB 100 and pass through the resin layers 111, 112, 113. There are embedded capacitors 130, embedded inductors 140 and embedded resistors 150 formed inside the intermediate layers 121, 122, wherein each embedded capacitor 130 includes an upper and lower electrode pads 132, 131 and a medium material 133 between the upper/lower electrode pads 132, 131. Since the PCB 100 is formed by laminated method, the lower electrode pad 131 needs to be placed on the upper surface of the lower resin layer 112 or 113 in advance and the upper electrode pad 132 needs to be placed on the lower surface of the upper resin layer 111 or 112 in advance prior to lamination. Also a plurality of traces 114 are formed on the upper surface of the resin layers 111, 112, 113. Accordingly, the compressing surface of the resin layers 111, 112, 113 is non-planar, resulting in a difficult lamination. The intermediate layers 121, 122 may easily cause overflow or insufficiency to produce bubbles with respect to the medium material 133. Referring to FIG. 1, there is no trace formed on the lower surface of the resin layers 111, 112, 113, except for the upper electrode pads 132 in order to slightly lessen laminating problem. But that will increase the number of wiring layers of the PCB 100, so that the PCB 100 is not suitable as a high density IC substrate. Furthermore, the resin layers 111, 112, 113 cannot be precisely positioned during laminating process, that is to say, the upper and lower electrode pads 132, 131 should be larger in design.